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BD4937G Datasheet(PDF) 5 Page - Rohm

Part # BD4937G
Description  Standard CMOS Voltage Detector IC
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

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Technical Note
5/9
BD48
□□G, BD48□□FVE, BD49□□G, BD49□□FVE series
www.rohm.com
2009.04 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
 Reference Data
Examples of Leading (TPLH) and Falling (TPHL) Output
Part Number
TPLH (
μs)
TPHL (
μs)
BD4845G/FVE
39.5
87.8
BD4945G/FVE
32.4
52.4
VDD=4.3V
5.1V
VDD=5.1V
4.3V
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
 Explanation of Operation
For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD48
□□G/FVE series uses an open drain
output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in
this case becomes VDD or the voltage of the other power supply].
Fig.12 (BD48
□□ Type Internal Block Diagram)
Fig.13 (BD49
□□ Type Internal Block Diagram)
 Timing Waveform
Example: the following shows the relationship between the input voltages VDD and the output voltage VOUT when the
input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig.12 and 13).
1
When the power supply is turned on, the output is unsettled from
after over the operating limit voltage (VOPL) until TPHL. There fore it
is possible that the reset signal is not outputted when the rise time of
VDD is faster than TPHL.
2
When VDD is greater than VOPL but less than the reset release
voltage (VS +
∆VS), the output voltages will switch to Low.
3
If VDD exceeds the reset release voltage (VS +
∆VS), then
VOUT switches from L to H.
4
If VDD drops below the detection voltage (VS) when the power
supply is powered down or when there is a power supply fluctuation,
VOUT switches to L (with a delay of TPHL).
5
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (
∆VS). The system
is designed such that the output does not flip-flop with power supply
fluctuations within this hysteresis width, preventing malfunctions due
to noise.
Vref
R1
R2
VDD
GND
Q1
VOUT
R3
RL
Vref
R1
R2
R3
Q2
Q1
VDD
VOUT
GND
VDD
VDET+ΔVDET
VDET
VOPL
0V
TPHL
VOUT
TPLH
TPHL
TPLH
VOL
VOH
Fig.14


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