Technical Note

4/14

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2010.09 - Rev.A

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BD9739KN,BD9740KN

(Unless otherwise specified, Ta = 25℃, VBAT = 3 V, VCC = 5 V, RT = 11 kΩ, CT = 180 pF, STB1 to STB7 = 3 V)

Parameter

Symbol

Limits

Unit

Conditions

Min.

Typ.

Max.

[Power on switching block] (BD9739KN)

SWOUT1

Output voltage

－

0.1

0.3

V

IO = 1 mA

Leak current

－

0

5

µA

STB = 0 V

SWOUT4

Output voltage

－

0.1

0.3

V

IO = 100 μA

Leak current

－

0

5

µA

STB = 0 V

SWOUT4,6

Output voltage

－

V

IO = 20 mA

VSWIN = 5 V

Leak current

－

0

5

µA

STB = 0 V

SWOUT7

Output voltage

－

V

IO = 10 mA

VSWIN = 10 V

Leak current

－

0

5

µA

STB = 0 V

[Soft start block] (BD9740KN)

Soft start time of CH4

1.8

3.6

6.0

mse

c

VCC = PVCC = 5V,

PVCCH = 5.0V

STB 0→3 V

Soft start time of CH2, 3

1.8

3.6

6.0

mse

c

VCC = PVCC = 5V,

STB = 3 V

INV4 = 0→1.2 V

CH2, CH3 soft start

INV4 threshold voltage at start

0.72

0.80

0.88

V

VCC = PVCC = 5 V

PVCCH = 5.0 V

[STB1 to STB7]

STB pin control voltage

ON

2.0

－

11

V

STB

OFF

-0.3

－

0.3

V

STB pin pull-down resistance

250

400

700

kΩ

STB

[Circuit current]

Standby current 1

(VBAT pin sink current)

－

－

5

µA

STB1 to STB7 = 0 V

Standby current 2

(VCC, PVCC pin sink current)

－

－

5

µA

STB1 to STB7 = 0 V

Circuit current at startup

(VBAT pin sink current)

－

30

100

mA

CT = 1.7 V

VCC = 0 V

Circuit current 1

(VBAT pin sink current)

－

100

300

µA

CT = 1.7 V

Circuit current 2

(VCC, PVCC pin sink current)

－

5

15

mA

CT = 1.7 V

INV = 2.5 V

Note: This IC is not designed to be radiation-resistant.

●

PVCCH and PVCCL input voltages

 Synchronous rectification channels with built-in FETs include, N-channel FETs

for both the high-side and low-side configuration. The driver block's power

source is supplied to the PVCCL pin for the low-side and the PVCCH pin for

the high-side. (For the BD9740KN, both sides are supplied to the PVCCH pin.)

In order to turn the FET on, a potential of at least 4 V must be supplied to the

PVCCL pin, and a potential of at least, DRAINH pin voltage + 4 V, must be

supplied to the PVCCH pin.

Note:

 The breakdown voltage for the PVCCL and PVCCH pins is 15 V.

For applications that with voltages exceeding 15 V, add a zener diode, or other

components, to provide overvoltage protection.

 Shorting the DRAINH pin with the ground, while a charge remains in the output

capacitor, may cause unexpected current flow, resulting in damage to the IC.

Add an external protective diode for applications where this possibility exists.

Fig. 1 Synchronous Rectification

Channel with Built-In FET

PGND

DRAINH

PVCCH

PVCCL

DRAINL

Vo