BD9775FV datasheet(4/15 Pages) ROHM

Part #	BD9775FV

Description	High Efficiency Step-down Switching Regulator Controller

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Manufacturer	ROHM [Rohm]

Direct Link	http://www.rohm.com

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Technical Note

4/14

www.rohm.com

2011.05 - Rev.A

BD9775FV

●

Pin Description

●

Pin No. / Pin Name

●

Block Diagram

No.

Name

Description

1

FB1

Error amplifier output pin(Channel 1)

2

INV1

Error amplifier negative input pin(Channel 1)

3

RT

Oscillator frequency adjustment pin

connected resistor

4

CT

Oscillator frequency adjustment pin

connected capacitor

5

FIN

Oscillator synchronization pulse signal input pin

6

GND

Low-noise ground

7

VREF

Reference voltage output pin

8

DTC1

Maximum duty and soft start adjustment pin

(Channel 1)

9

DTC2

Maximum duty and soft start adjustment pin

(Channel 2)

10

INV2

Error amplifier negative input pin(Channel 2)

11

FB2

Error amplifier output pin(Channel 2)

12

CTL1

Enable/stand-by control input(Channel 1)

13

CTL2

Enable/stand-by control input(Channel 2)

14

VCC

Main power supply pin

15

SYNC Synchronous rectification timing adjustable pin

16

PGND

Power ground

(connected low-side gate driver and digital ground)

17

OUT2L

Low-side ( synchronous rectifier ) gate driver

output pin(Channel 2)

18

VREGA Connected capacitor for internal regulator

19

SCP

Delay time of short circuit protection adjustment

pin connected capacitor

20

VS2

Over current detection voltage monitor pin

(connected FET drain, Channel 2)

21

CL2

Over current detection voltage adjustment pin

connected capacitor and resistor(Channel 2)

22

PVCC2

High-side gate driver power supply input

(Channel 2)

23

OUT2H High-side gate driver output pin(Channel 2)

24

VREGB Connected capacitor for internal regulator

25

OUT1

High-side gate driver output pin(Channel 1)

26

PVCC1 High-side gate driver power supply input

(Channel 1)

27

CL1

Over current detection voltage adjustment pin

connected capacitor and resistor(Channel 1)

28

VS1

Over current detection voltage monitor pin

(connected FET drain, Channel 1)

28

27

26

25

24

23

22

21

20

19

18

1

2

3

4

5

6

7

8

9

10

11

FB1

INV1

RT

CT

Fin

GND

VREF

DTC1

DTC2

INV2

FB 2

VS1

CL1

PVCC1

OUT1

VREGB

OUT2H

PVCC2

CL2

VS2

SCP

VREGA

17

16

15

12

13

14

CTL1

CTL2

VCC

OUT2L

PGND

SYNC

Fig.1 Pin Description

Fig.2 Block Diagram

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