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ISL80102 Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL80102 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 15 page ISL80102, ISL80103 3 FN6660.2 March 24, 2011 Pin Configuration ISL80102, ISL80103 (10 LD 3x3 DFN) TOP VIEW 2 3 4 1 5 9 8 7 10 6 VOUT VOUT SENSE/ADJ PG GND VIN VIN DNC ENABLE SS Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2 VOUT Output voltage pin. 3 SENSE/ADJ Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT. 4PG VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used. 5GND GND pin. 6 SS External cap adjusts in-rush current. 7ENABLE VIN independent chip enable. TTL and CMOS compatible. 8 DNC Do not connect this pin to ground or supply. Leave floating. 9, 10 VIN Input supply pin. EPAD EPAD at ground potential. Soldering it directly to GND plane is optional. Typical Application FIGURE 2. TYPICAL APPLICATION DIAGRAM ISL80102, ISL80103 VIN 9 VIN 10 ENABLE 7 SS 6 GND 2.5V ±10% CIN 10µF VIN *CSS 5 PG 4 VOUT 1 VOUT 2 VOUT 1.8V COUT 10µF RPG 100kΩ ADJ 3 PGOOD R1 10kΩ R4 1.0kΩ **CPB 1500pF EN OPEN DRAIN COMPATIBLE *CSS is optional, (see Note 12) on page 5. **CPB is optional. See “Functional Description” on page 12 for more information. R3 2.61kΩ |
Similar Part No. - ISL80102_11 |
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Similar Description - ISL80102_11 |
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