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TPD4E001DRLR Datasheet(PDF) 2 Page - Texas Instruments |
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TPD4E001DRLR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page IO3 IO4 GND IO2 IO1 V CC TPD4E001 SLLS682F – JULY 2006 – REVISED MAY 2011 www.ti.com Figure 1. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION DRS/DRL NO. DBV/DCK NO. NAME FUNCTION 1, 2, 4, 5 1, 3, 4, 6 IOx ESD-protected channel 3 2 GND Ground 6 5 VCC Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor. Exposed Thermal Pad (DRS package N/A Exposed thermal pad. Connect to GND or leave floating. only) Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC –0.3 7 V VI/O IO voltage tolerance –0.3 VCC + 0.3 V Tstg Storage temperature range –65 150 °C TJ Junction temperature 150 °C Infrared (15 s) 220 Bump temperature (soldering) °C Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) 300 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Copyright © 2006–2011, Texas Instruments Incorporated |
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