peaking in the PLL passband region to less than 0.1dB.

≤ K/100.

The three-level GSEL pins (see

Functional Diagram)

the GSEL pins. A more detailed analysis of the loop filter

is located in application note HFDN-13.0 on

www.maxim-ic.com.

Setting the Higher-Order Poles

Spurious noise is generated by the phase detector

digital phase detector by placing a higher-order pole

(HOP) at a frequency much less than the compare fre-

quency. The HOP should, however, be placed high

enough in frequency that it does not decrease the over-

all loop-phase margin and impact jitter peaking. These

two conditions can be met by selecting the HOP fre-

the loop bandwidth.

The HOP can be implemented either by providing a

directly on the VCO tuning port, which produces a pole at

noise in the PLL, but it may still be necessary to provide

to prevent clipping in the op amp.

Setting the Optional Output

The MAX3670 optional clock output can be set to bina-

ry subdivisions of the main clock frequency. The PSEL1

and PSEL2 pins control the binary divisions. Table 4

shows the pin configuration along with the possible

divider ratios.

Applications Information

PECL Interfacing

The MAX3670 outputs (MOUT+, MOUT-, POUT+,

POUT-) are designed to interface with PECL signal lev-

els. It is important to bias these ports appropriately. A

circuit that provides a Thévenin equivalent of 50

Ω to

sion lines with proper termination. To ensure best per-

formance, the differential outputs must have balanced

loads. It is important to note that if optional clock output

is not used, it should be left unconnected to save

power (see Figure 2).

f

RC

π

1

2

33

f

kC

πΩ

1

220

2

()(

)

Low-Jitter 155MHz/622MHz

Clock Generator

_______________________________________________________________________________________

9

INPUT

PIN

GSEL1

INPUT

PIN

GSEL2

INPUT

PIN

GSEL3

KPD

(µA/UI)

DIVIDER

RATIO

20

1

OPEN

20

2

GND

20

4

OPEN

20

8

OPEN

OPEN

20

16

GND

OPEN

20

32

GND

20

64

OPEN

GND

20

128

GND

GND

20

256

GND

20

512

OPEN

GND

20

1024

OPEN

5

1

OPEN

OPEN

5

2

GND

OPEN

5

4

OPEN

OPEN

5

8

OPEN

OPEN

OPEN

5

16

GND

OPEN

OPEN

5

32

GND

OPEN

5

64

OPEN

GND

OPEN

5

128

GND

GND

OPEN

5

256

OPEN

GND

5

512

OPEN

OPEN

GND

5

1024

Table 3. Gain Logic Pin Setup

INPUT PIN

PSEL1

INPUT PIN

PSEL2

VCO TO POUT

DIVIDER RATIO

1

GND

2

GND

4

GND

GND

8

Table 4. Setting the Optional Clock

Output Driver