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Applications Information

Simplified Block Diagram of 5-Bit Counter

Asynchronous Programming

The 5-Bit programmable counter counts-down from the programmed value of the data bits to zero and issues an

output pulse at the end of each cycle. Settling time of the programmable 5-Bit counter is defined as the maximum

time required for the counter to change the division ratio N to a new value after the data bits have settled. The worst

case settling time occurs if the data bits A0 thru A4 are changing during the load cycle. Under this condition, the

data bits may potentially be erroneous when they are clocked in and in the worst case could be all 1’s, requiring 32

clock cycles until the correct data is re-loaded into the flip flops. The worst case asynchronous settling time can be

calculated as follows:

T

SETTLING MAX

= 32/f

IN

(For Asynchronous Programming)

As an example, if the input frequency is 1 GHz, the maximum settling time is 32 nS

v03.0808

2.8 GHz INTEGER-N SYNTHESIZER

(N = 2 - 32)