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ICS5342 Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS5342 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 35 page ICS5342 GENDAC 8 Differential output delay ∆t CHAV 2 2 2 ns note G WR* pulse width low tWLWH 50 50 50 ns RD* pulse width low tRLRH 50 50 50 ns Register select setup time tSVWL 10 10 10 ns write cycle Register select setup time tSVRL 10 10 10 ns read cycle Register select hold time tWLSX 10 10 10 ns write cycle Register select hold time tRLSX 10 10 10 ns read cycle WR* data setup time tDVWH 10 10 10 ns WR* data hold time tWHDX 10 10 10 ns Output turn-on delay tRLQX 555ns RD* enable access time tRLQV 40 40 40 ns Output hold time tRHQX 333ns Output turn-off delay tRHQZ 20 20 20 ns note H Successive write inter- val tWHWL1 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I WR* followed by read interval tWHRL1 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I Successive read interval tRHRL1 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I RD* followed by write interval tRHWL1 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I WR* after color write tWHWL2 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I RD* after color write tWHRL2 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) cycle note I RD* after color read tRHRL2 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) cycle note I WR* after color read tRHWL2 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) cycle note I RD* after read address write tWHRL3 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) cycle note I SENSE* output delay tSOD 11 1 µs XIN input clock rise time tXCLKR* 15 15 15 ns TTL levels AC Electrical Characteristics (note: J) Parameter Symbol 80 MHZ 110MHz 135Mhz Units Test Conditions Min Max Min Max Min Max ICS5342 16-Bit Integrated Clock-LUT-DAC TSD IDT™ / ICS™ 16-Bit Integrated Clock-LUT-DAC ICS5342 8 |
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