ICS9148-20 datasheet(2/11 Pages) IDT

Part #	ICS9148-20

Description	Pentium/ProTM System Clock Chip

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Manufacturer	IDT [Integrated Device Technology]

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2

ICS9148-20

Pin Descriptions

Select Functions

Notes:

1. TCLK is a test clock driven on the X1 (crystal in

pin) input during test mode.

2. -0.5% modulation down spread from the selected

frequency.

Functionality

CPU

PCI,

PCI_F

REF

IOAPIC

48 MHz

Selection

Tristate

HI - Z

Testmode

TCLK/2

1

TCLK/61

TCLK1

TCLK/21

Spread Spectrum

Modulated2

14.318MHz

48.0MHz

SEL 100/66#

FS1

FS0

Function

0

Tri-State

00

1

(Reserved)

01

0

(Reserved)

0

1

Active 66.6MHz CPU, 33.3 PCI

10

0

Test Mode

10

1

(Reserved)

11

0

(Reserved)

1

Active 100MHz CPU, 33.3 PCI

P IN NUM B E R

P IN N A M E

TYP E

DE S CRIP T IO N

1, 2, 47

R E F (0 :2 )

O U T

14.318M H z clock output

3

GND1

P W R

G rou n d fo r R E F o u tp uts

4X 1

IN

X TA L _IN 14.318M H z C rystal in pu t, has internal 33pF

lo ad ca p an d fe ed b ack resisto r from X 2

5

X 2

O U T

X TA L _O U T C rystal output, has in tern al lo ad cap 33pF

6, 1 2 , 1 8

GND2

P W R

G rou n d fo r P C I o u tp uts

7

P C IC L K _F

O U T

Free R unning PC I output

8, 10, 11, 13, 14, 16 ,

17

P C IC LK (0:6)

O U T

P C I clo ck o u tp uts. TTL com p atible 3.3 V

9, 15

V D D 2

P W R

Pow er for P C IC L K outputs, no m inally 3.3V

19, 33

V D D

P W R

Iso late d pow er fo r co re, nom in ally 3.3V

20, 32

G N D

P W R

Iso late d ground fo r co re

21

VDD3

P W R

P ow er for 4 8 M Hz o utpu ts, n o m in ally 3 .3V

22, 23

48M H z (0 :1 )

O U T

48 M H z outputs

2 4

GND3

P W R

G rou n d fo r 4 8M H z o u tp uts

25

SE L 1 00 /66.6#

IN

Select pin for en ab ling 100M H z or 66.6M H z

H = 100M H z, L = 66 .6M H z (P C I alw ays synchron ou s

33 .3M H z)

26, 27

FS (0 :1 )

IN

F requ en cy S elect pins

28

S P R E A D #

IN

E n ab les S p re ad S p ectrum feature w h en L O W

2 9

P D #

IN

P ow ers d ow n ch ip , active low

3 0

C P U_ S T OP #

IN

H alts C P U c lo cks at log ic "0 " level wh en low

31

P C I_S TO P #

IN

H alts P C I B us at log ic " 0" level w hen low

3 7, 4 1

VDDL 2

P W R

P ower for CP U o utpu ts, no m in ally 2 .5V

34 , 38

G N D L 2

P W R

G round fo r C P U outputs.

35, 36, 39, 40

C P U C L K (3 :0 )

O U T

C P U and H o st clock outputs @ 2.5V

42

N /C

-

N ot interna lly co nn ected

43

GNDL 1

P W R

Grou n d fo r IO AP IC o u tp uts

44 , 4 5

IO A P IC (0 :1 )

O U T

IO A P IC o utpu ts (1 4.3 18 M H z) @ 2.5 V

4 6

VDDL 1

P W R

P ower for IO AP IC o utpu ts, n o m in ally 2 .5V

4 8

VDD1

P W R

S u p ply fo r R E F (0 :1 ), X1 , X2 , n o m in al 3 .3V

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