MC74HCU04

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Guaranteed Limit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 2)

2.0

4.5

6.0

80

16

14

100

20

17

120

24

20

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Inverter)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Inverter)*

15

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Figure 1. Switching Waveforms

tr

VCC

GND

90%

50%

10%

90%

50%

10%

INPUT A

OUTPUT Y

tPHL

tPLH

tTHL

tTLH

* Includes all probe and jig capacitance

Figure 2. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

LOGIC DETAIL

(1/6 of Device Shown)

tf

A

VCC

Y