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GS1545-CQRE3 Datasheet(PDF) 8 Page - Gennum Corporation |
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GS1545-CQRE3 Datasheet(HTML) 8 Page - Gennum Corporation |
8 / 19 page GENNUM CORPORATION 522 - 28 - 05 8 of 19 32, 33 SP_VEE Power Input Negative Supply. Most negative power supply connection for the parallel output stage. 34 PCLK_OUT TTL Output Output Clock. The device uses PCLK_OUT for clocking the output data stream from DATA_OUT[19:0]. This clock is also used to clock the data into the GS1500 HDTV Deformatter or GS1510 Deformatter. 35 PCLK_VCC Power Input Positive Supply. Most positive supply connection for parallel clock output stage. 36 PCLK_VEE Power Input Negative Supply. Most negative power supply connection for parallel clock output stage. 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 53, 54, 55, 56, 59, 60, 61, 62, 63, 64 DATA_OUT[19:0] TTL Output Parallel Data Output Bus. The device outputs a 20 bit parallel data stream running at 74.25 or 74.25/1.001MHz on DATA_OUT[19:0]. DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB. 72 LFA_VCC Power Input Positive Supply. Loop filter most positive power supply connection. 73 LFA Analog Output Control Signal Output. Control voltage for GO1515 VCO. 74 LBCONT Analog Input Control Signal Input. Used to provide electronic control of Loop Bandwidth. 75 LFA_VEE Power Input Negative Supply. Loop filter most negative power supply connection. 76 DFT_VEE Power Input Most negative power supply connection - enables the jitter demodulator functionality. This pin should be connected to ground. If left floating, the DM function is disabled resulting in a current saving of 340µA. 79, 80 DM, DM Analog Output Test Signal. Used for manufacturing test only. These pins must be floating for normal operation. 81, 85 LFS, LFS Analog Input Loop Filter Connections. 86 IJI Analog Output Status Signal Output. Approximates the amount of excessive jitter on the incoming DDI and DDI input. 89 VCO Analog Input Control Signal Input. Input pin is AC coupled to ground using a 50 Ω transmission line. 91 VCO Analog Input Control Signal Input. Voltage controlled oscillator input. This pin is connected to the output pin of the GO1515 VCO. This pin must be connected to the GO1515 VCO output pin via a 50 Ω transmission line. 93, 96 PLCAP, PLCAP Analog Input Control Signal Input. Phase lock detect time constant capacitor. 98 PLL_LOCK TTL Output Status Indicator Signal. This signal is a combination (logical AND) of the carrier detect and phase lock signals. When input is present and PLL is locked, the PLL_LOCK goes high and the outputs are valid. When the PLL_LOCK output is low the data output is muted (latched at the last state). PLL_LOCK is independent of the BYPASS signal. 105 BYPASS TTL Input Control Signal Input. Selectable input that controls whether the input signal is reclocked or passed through the chip. When BYPASS is high; the input signal is reclocked. When BYPASS is low; the input signal is passed through the chip and not reclocked. Muting does not effect bypassed signal. PIN DESCRIPTIONS (Continued) NUMBER SYMBOL LEVEL TYPE DESCRIPTION |
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