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GS9091B Datasheet(PDF) 7 Page - Gennum Corporation |
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GS9091B Datasheet(HTML) 7 Page - Gennum Corporation |
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7 / 71 page  GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 7 of 71 Proprietary & Confidential A10, B10, C10, D10, E10, F10, G10, H10, J10, K10 DOUT[9:0] Synchronous with RD_CLK or PCLK Output PARALLEL VIDEO DATA BUS Signal levels are LVCMOS / LVTTL compatible. When the internal FIFO is enabled and configured for either video mode or DVB-ASI mode, parallel data will be clocked out of the device on the rising edge of RD_CLK. When the internal FIFO is in bypass mode, parallel data will be clocked out of the device on the rising edge of PCLK. DOUT9 is the MSB and DOUT0 is the LSB. B1 LF- Analog Input Loop filter component connection. Connect to LF+ through a 4.4nF capacitor. B2 PLL_VDD Analog Input Power Power supply connection for phase-locked loop. Connect to +1.8V DC. B3 PLL_GND Analog Input Power Ground connection for phase-locked loop. Connect to GND. B4 VCO_GND Analog Input Power Ground connection for Voltage-Controlled-Oscillator. Connect to GND. B6 FW_EN Non Synchronous Input CONTOL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to enable or disable the noise immune flywheel of the device. When set HIGH, the internal flywheel is enabled. This flywheel is used in the extraction of timing signals, the generation of TRS signals, the automatic detection of video standards, and in manual switch line lock handling. When set LOW, the internal flywheel is disabled. Timing based TRS errors will not be detected. B7, J6 CORE_VDD Non Synchronous Input Power Power supply for digital logic blocks. Connect to +1.8V DC. B8 SMPTE_BYPASS Non Synchronous Input / Output CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. This pin is an input set by the application layer in Manual mode, and an output set by the device in Auto mode. Auto Mode (AUTO/MAN = HIGH): The SMPTE_BYPASS pin will be HIGH only when the device has locked to a SMPTE compliant data stream. It will be LOW otherwise. When the pin is LOW, no I/O processing features are available. Manual Mode (AUTO/MAN = LOW): When the application layer sets this pin HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When SMPTE_BYPASS is set LOW, the device will not support the descrambling, decoding, or word alignment of received SMPTE data. No I/O processing features will be available. Table 1-1: Ball List and Description (Continued) Ball Name Timing Type Description |
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