1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CS

D13

SDO

t

SU1

t

D1

t

H1

t

D2

t

D3

Sample

N

Sample

N+1

t

ACQ

t

CONV

1/f

SAMPLE

DatafromSampleN

1

-

t

D4

t

WL

t

WH

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

t

W1

ADS7945

ADS7946

www.ti.com

SBAS539B

– JUNE 2011 – REVISED SEPTEMBER 2011

PARAMETER MEASUREMENT INFORMATION

TIMING DIAGRAM: ADS7945, ADS7946

PARAMETER

MIN

TYP

MAX

UNIT

Conversion time

16

SCLK

Acquisition time

80

ns

SCLK = 40 MHz,

Sample rate (throughput rate)

2

MSPS

16-clock frame

Pulse width CS high

25

ns

DVDD = 1.8 V

14.5

ns

Delay time, CS low to first data (D0-15) out

DVDD = 3 V

12.5

ns

DVDD = 5 V

8.5

ns

DVDD = 1.8 V

3.5

ns

Setup time, CS low to first rising edge of SCLK

DVDD = 3 V

3.5

ns

DVDD = 5 V

3.5

ns

DVDD = 1.8 V

11

ns

(3)

Delay time, SCLK falling to SDO

DVDD = 3 V

9

ns

DVDD = 5 V

7.1

ns

DVDD = 1.8 V

4

ns

Hold time, SCLK falling to data valid

DVDD = 3 V

3

ns

DVDD = 5 V

2

ns

DVDD = 1.8 V

15

ns

Delay time, CS high to SDO 3-state

DVDD = 3 V

12.5

ns

DVDD = 5 V

8.5

ns

Delay time CS rising edge from conversion end

10

ns

Pulse duration, SCLK high

8

ns

Pulse duration, SCLK low

8

ns

SCLK frequency

40

MHz

Setup time, PDEN high to CS rising edge

2

ns

(refer to Figure 84 and Figure 85)

Hold time, CS rising edge to PDEN falling edge (refer to Figure 84)

20

ns

(1)

(2)

1.8 V specifications apply from 1.65 V to 2 V; 3 V specifications apply form 2.7 V to 3.6 V; 5 V specifications apply from 4.75 V to

5.25 V.

(3)

With 20 pF load.

Copyright

© 2011, Texas Instruments Incorporated

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