 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
OMAP-L132 Datasheet(PDF) 6 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
OMAP-L132 Datasheet(HTML) 6 Page - Texas Instruments |
|
|
6 / 227 page  OMAP-L132 SPRS762 – AUGUST 2011 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 2-1. Characteristics of OMAP-L132 HARDWARE FEATURES OMAP-L132 DDR2, 16-bit bus width, up to 150 MHz DDR2/mDDR Controller Mobile DDR, 16-bit bus width, up to 133 MHz Asynchronous (8/16-bit bus width) RAM, Flash, EMIFA 16-bit SDRAM, NOR, NAND Flash Card Interface 2 MMC and SD cards supported. 64 independent channels, 16 QDMA channels, EDMA3 2 channel controllers, 3 transfer controllers 4 64-Bit General Purpose (each configurable as 2 separate Timers 32-bit timers, one configurable as Watch Dog) Peripherals UART 3 (each with RTS and CTS flow control) Not all peripherals pins SPI 2 (Each with one hardware chip select) are available at the same time (for more I2C 2 (both Master/Slave) detail, see the Device Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) Configurations section). Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16) 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface) 4 Single Edge, 4 Dual Edge Symmetric, or eHRPWM 2 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY General-Purpose Input/Output Port 9 banks of 16-bit PRU Subsystem (PRUSS) 2 Programmable PRU Cores Size (Bytes) 488KB RAM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) DSP Memories can be made accessible to ARM, EDMA3, and other peripherals. On-Chip Memory Organization ARM 16KB I-Cache 16KB D-Cache 8KB RAM (Vector Table) 64KB ROM ADDITIONAL SHARED MEMORY 128KB RAM C674x CPU ID + CPU Control Status Register (CSR.[31:16]) 0x1400 Rev ID C674x Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F 674x DSP 200 MHz (1.2V) CPU Frequency MHz ARM926 200 MHz (1.2V) Core (V) 1.2 V nominal Voltage I/O (V) 1.8V or 3.3 V Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT) 6 Device Overview Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): OMAP-L132 |
Similar Part No. - OMAP-L132 |
|
Similar Description - OMAP-L132 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
