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TMS320DM8148_1109 Datasheet(PDF) 43 Page - Texas Instruments

Part # TMS320DM8148_1109
Description  TMS320DM814x DaVinci Digital Media Processors
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM8148_1109 Datasheet(HTML) 43 Page - Texas Instruments

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TMS320DM8148, TMS320DM8147, TMS320DM8146
www.ti.com
SPRS647B
– MARCH 2011 – REVISED SEPTEMBER 2011
Table 3-1. Boot Configuration Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
MUXED
DESCRIPTION
NAME
NO.
XIP (NOR) on GPMC Configuration. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, when the XIP (MUX0), XIP (MUX1),
XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode
is selected (see Table 4-1), BTMODE[10] is sampled to
GPMC
select between GPMC pin muxing options A or B shown
GPMC_D[10]/
DIS
Y26
I
PINCNTL99
in Table 4-2, XIP (on GPMC) Boot Options [Muxed or
BTMODE[10]
DVDD_GPMC
DSIS: PIN
Non-Muxed].
0 = GPMC Option A
1 = GPMC Option B
After reset, this pin functions as GPMC multiplexed
data/address pin 10 (GPMC_D[10]).
GPMC
Ethernet PHY Configuration. These pins are multiplexed
GPMC_D[9]/
DIS
AB28
I
PINCNTL98
between ARM Cortex-A8 boot mode and
BTMODE[9]
DVDD_GPMC
DSIS: PIN
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, when EMAC bootmode is selected
(see Table 4-1), BTMODE[9:8] pins are sampled to
determine the function of the Ethernet PHY Mode
selection.
00 = MII (GMII)
01 = RMII
GPMC
10 = RGMII
GPMC_D[8]/
DIS
Y27
I
PINCNTL97
11 = Reserved
BTMODE[8]
DVDD_GPMC
DSIS: PIN
For more detailed information on the EMAC PHY boot
modes and the EMAC pin functions selected, see
Section 4.2.6, Ethernet PHY Mode Selection.
After reset, these pins function as GPMC multiplexed
data/address pins 9 and 8 (GPMC_D[9] and
GPMC_D[8]).
GPMC
GPMC_D[7]/
DIS
Reserved Boot Pins. These pins are multiplexed between
V25
I
PINCNTL96
BTMODE[7]
DVDD_GPMC
ARM Cortex-A8 boot mode and General-Purpose
DSIS: PIN
Memory Controller (GPMC) peripheral functions.
GPMC
GPMC_D[6]/
DIS
U25
I
PINCNTL95
For proper device operation at reset, these pins should
BTMODE[6]
DVDD_GPMC
DSIS: PIN
be externally pulled low.
GPMC
After reset, these pins function as GPMC multiplexed
GPMC_D[5]/
DIS
AA28
I
PINCNTL94
data/address pins 10 through 5 (GPMC_D[7:5]).
BTMODE[5]
DVDD_GPMC
DSIS: PIN
GPMC
GPMC_D[4]/
DIS
ARM Cortex-A8 Boot Mode Configuration Bits. These
V26
I
PINCNTL93
BTMODE[4]
DVDD_GPMC
pins are multiplexed between ARM Cortex-A8 boot mode
DSIS: PIN
and the General-Purpose Memory Controller (GPMC)
GPMC
peripheral functions.
GPMC_D[3]/
DIS
W27
I
PINCNTL92
BTMODE[3]
DVDD_GPMC
At reset, the boot mode inputs BTMODE[4:0] are
DSIS: PIN
sampled to determine the ARM boot configuration. For
GPMC
GPMC_D[2]/
DIS
more details on the types of boot modes supported, see
V27
I
PINCNTL91
BTMODE[2]
DVDD_GPMC
Section 4.2, Boot Modes, of this document, along with
DSIS: PIN
the TMS320DM814x ROM Code Memory and Peripheral
GPMC
Booting chapter of the TMS320DM814x DaVinci
™ Digital
GPMC_D[1]/
DIS
Y28
I
PINCNTL90
Media Processors Technical Reference Manual
BTMODE[1]
DVDD_GPMC
DSIS: PIN
(Literature Number: SPRUGZ8).
GPMC
After reset, these pins function as GPMC multiplexed
GPMC_D[0]/
DIS
U26
I
PINCNTL89
data/address pins 4 through 0 (GPMC_D[4:0]).
BTMODE[0]
DVDD_GPMC
DSIS: PIN
Copyright
© 2011, Texas Instruments Incorporated
Device Pins
43
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