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TMS320DM8148_1109 Datasheet(PDF) 1 Page - Texas Instruments

Part # TMS320DM8148_1109
Description  TMS320DM814x DaVinci Digital Media Processors
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM8148_1109 Datasheet(HTML) 1 Page - Texas Instruments

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TMS320DM8148, TMS320DM8147, TMS320DM8146
www.ti.com
SPRS647B
– MARCH 2011 – REVISED SEPTEMBER 2011
TMS320DM814x DaVinci
Digital Media Processors
Check for Samples: TMS320DM8148, TMS320DM8147, TMS320DM8146
1
High-Performance System-on-Chip (SoC)
1.1
Features
12
– 32K-Byte L1P RAM/Cache With EDC
• High-Performance DaVinci™ Digital Media
Processors
– 32K-Byte L1D RAM/Cache
– Up to 1-GHz ARM® Cortex™-A8 RISC MPU
– 256K-Byte L2 Unified Mapped RAM/Caches
With ECC
– Up to 750-MHz C674x™ VLIW DSP
• DSP/EDMA Memory Management Unit
– Up to 6000/4500 C674x™ MIPS/MFLOPS
(DEMMU)
– Fully Software-Compatible with C67x+™,
– Maps C674x DSP and EDMA TC Memory
C64x+
Accesses to System Addresses
• ARM® Cortex™-A8 Core
• 128K-Bytes On-Chip Memory Controller
– ARMv7 Architecture
(OCMC) RAM
In-Order, Dual-Issue, Superscalar
• Imaging Subsystem (ISS)
Microprocessor Core
– Camera Sensor Connection
NEON
™ Multimedia Architecture
Parallel Connection for Raw (up to 16-Bit)
Supports Integer and Floating Point
and BT.656/BT.1120 (8-/16-bit)
Jazelle
® RCT Execution Environment
– Image Sensor Interface (ISIF) for Handling
• ARM® Cortex™-A8 Memory Architecture
Image/Video Data From the Camera Sensor
– 32K-Byte Instruction and Data Caches
– Resizer
– 512K-Byte L2 Cache
Resizing Image/Video From 1/16x to 8x
– 64K-Byte RAM, 48K-Byte Boot ROM
Generating Two Different Resizing
• TMS320C674x™ Floating-Point VLIW DSP
Outputs Concurrently
– 64 General-Purpose Registers (32-Bit)
• Programmable High-Definition Video Image
– Six ALU (32-/40-Bit) Functional Units
Coprocessing (HDVICP v2) Engine
Supports 32-Bit Integer, SP (IEEE Single
– Encode, Decode, Transcode Operations
Precision/32-Bit) and DP (IEEE Double
– H.264, MPEG2, VC1, MPEG4, SP/ASP,
Precision/64-Bit) Floating Point
JPEG/MJPEG
Supports up to Four SP Adds Per Clock
• Media Controller
and Four DP Adds Every Two Clocks
– Controls the HDVPSS, HDVICP2, and ISS
Supports up to Two Floating-Point (SP or
• SGX530 3D Graphics Engine
DP) Approximate Reciprocal or Square
– Delivers up to 18 MPoly/sec
Root Operations Per Cycle
– Universal Scalable Shader Engine
– Two Multiply Functional Units
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
Mixed-Precision IEEE Floating-Point
OpenVG 1.0, OpenMax API Support
Multiply Supported up to:
– Advanced Geometry DMA Driven Operation
– 2 SP x SP → SP Per Clock
– Programmable HQ Image Anti-Aliasing
– 2 SP x SP → DP Every Two Clocks
• Endianness
– 2 SP x DP → DP Every Three Clocks
– ARM/DSP Instructions/Data – Little Endian
– 2 DP x DP → DP Every Four Clocks
• HD Video Processing Subsystem (HDVPSS)
Fixed-Point Multiply Supports Two 32 x
– Two 165 MHz HD Video Capture Inputs
32 Multiplies, Four 16 x 16-bit Multiplies
including Complex Multiplies, or Eight 8 x
One 16/24-bit Input, Splittable into Dual
8-Bit Multiplies per Clock Cycle
8-bit SD Capture Ports
• C674x™ Two-Level Memory Architecture
One 8/16/24-bit Input
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
Copyright
© 2011, Texas Instruments Incorporated
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.


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