LC875BP4A/875BM2A/875BJ0A/875BH4A

No.7972-3/25

Serial Interface

• SIO 0 : 8-bit synchronous serial interface

1. LSB first/MSB first-function available

2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)

3. Consecutive automatic data communication (1 to 256-bits)

• SIO 1 : 8-bit asynchronous/synchronous serial interface

Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)

Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tCYC)

Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)

Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)

• SIO2 : 8-bit synchronous serial interface

1. LSB-first

2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)

3. Consecutive automatic data communication (1 to 32 bytes)

UART :2-channels

1. Full duplex

2. 7/8/9 bit data bits selectable

3. 1stop bit

4. built-in baudrate generator

AD Converter

• 12-channel × 8-bit AD converter

PWM

• 4-channel × synchronous variable 12-bit PWM

Remote Receiver Circuit (share with P73/INT3/T0IN terminal)

• Noise rejection function (The filtering time of the noise rejection filter (1tCYC/32 tCYC/128 tCYC) can be switched

by program.)

Watchdog Ttimer

• External RC circuit is required.

• Interrupt or system reset is activated when the timer overflows.

Interrupts

• 27-source and 10-vectored interrupt function :

1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible.

During interrupt handling, an equal or lower level interrupt request is refused.

2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes

precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.

No.

Vector

Selectable Level

Interrupt Signal

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4

4

0001BH

H or L

INT3/INT5/base timer

5

00023H

H or L

T0H

6

0002BH

H or L

T1L/T1H

7

00033H

H or L

SIO0/UART1, 2 receive

8

0003BH

H or L

SIO1/SIO2/UART1, 2 transmit

9

00043H

H or L

ADC/T6/T7/PWM4, PWM5

10

0004BH

H or L

Port 0/T4/T5/PWM0, PWM1

• Priority Level : X > H > L

• For equal priority levels, vector with lowest address takes precedence.