Second byte

Register content

DA0 to DA7

Register name

State

Function

Note

7c7

0

1

6c6

0

1

5c5

0

1

4c4

0

1

Character code (from 00 to FF (hexadecimal))

3c3

0

1

2c2

0

1

1c1

0

1

0c0

0

1

Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.

3

COMMAND2: Vertical Display Position Setting Command

First byte

Register content

DA0 to DA7

Register name

State

Function

Note

7—

1

6—

0

The command 2 identification code:

5—

1

sets the vertical display position.

4—

0

3

SZ21

0

1

Character size for the second line

2

SZ20

0

1

1

SZ11

0

1

Character size for the first line

0

SZ10

0

1

Second byte

Register content

DA0 to DA7

Register name

State

Function

Note

7—

0

Second byte identification code

6—

0

5

VP5

0

The vertical display start position is given by

(MSB)

1

4

VP4

0

1

where H is the horizontal synchronization pulse period.

3

VP3

0

The six bits VP0 to VP5 specify the

1

vertical display start position.

2

VP2

0

The weight of the lsb is 1

× H.

1

1

VP1

0

1

0

VP0

0

(LSB)

1

Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.

No. 4846-9/21

LC74761, LC74761M

SZ20

SZ21

01

0

Normal size

Double size

1

Triple size

Normal size

SZ10

SZ11

01

0

Normal size

Double size

1

Triple size

Normal size

5

VS = H

n = 0

HSYNC

VS

Character

display area

HS

VSYNC