Two enable comparators (CEN1 and CEN2) are avail-

able to control and sequence the two PWM sections

through the enable (EN1 or EN2) inputs. An oscillator,

with an externally programmable frequency generates

two clock pulse trains and two ramps for both PWM

sections. The two clocks and the two ramps are 180°

out of phase with each other.

A linear regulator (REG) generates the 5V to supply the

device. This regulator has the output-current capability

necessary to provide for the MAX15034’s internal

circuitry and the power for the external MOSFET’s gate

drivers. Internal UVLO circuitry ensures that the

age levels to guarantee safe operation of the IC and of

the power MOSFETs.

Finally, a thermal-shutdown feature protects the device

during thermal faults and shuts down the MAX15034

when the die temperature exceeds +160°C.

16

17

18

19

BST1

DH1

LX1

DL1

20

27

26

25

24

23

BST2

DH2

LX2

DL2

PGND

2 CSP2

1 CSN2

13 CSP1

14 CSN1

CA1

11

EAN1

6

AVGLIMIT

AGND

8

EN1

15

EN2

28

CA2

CPWM1

CPWM2

7 RT/CLKIN

CEA1

CEA2

12

EAOUT1

9

MODE

3

EAOUT2

5

CLP2

10

CLP1

22

IN

21

REG

1.225V

1.225V

THERMAL

SHUTDOWN

MUX

4

EAN2

CEN1

VEA1

DF1 AND

HICCUP

LOGIC

EXTERNAL FREQUENCY SYNC

0

°

CONTROL

AND DRIVER

LOGIC 1

CONTROL

AND DRIVER

LOGIC 2

DF2 AND

HICCUP

LOGIC

OSCILLATOR

AND PHASE

SPLITTER

180

°

RAMP

FOR INTERNAL

BIASING

UVLO

VEA2

CEN2

RAMP

Figure 1. Block Diagram

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________

11