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ADS1131ID Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1131ID Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 20 page  17 1 18 19 16 15 0 Data 19thSCLKtoForce /DOUTHigh DRDY DataReady NewDataReady DRDY/DOUT SCLK DRDY/DOUT 17 16 15 1 18 0 17 SCLK StandbyMode DataReady t DSS t STANDBY t S_RDY StartConversion ADS1131 www.ti.com SBAS449B – JULY 2009 – REVISED SEPTEMBER 2011 STANDBY MODE When tSTANDBY has passed with SCLK held high, Standby mode dramatically reduces power Standby mode activates. DRDY/DOUT stays high consumption by shutting down most of the circuitry. In when Standby mode begins. SCLK must remain high Standby mode, the entire analog circuitry is powered to stay in Standby mode. To exit Standby mode down and only the clock source circuitry is awake to (wakeup), set SCLK low. The first data after exiting reduce the wake-up time from the Standby mode. To Standby mode are valid. enter Standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 8. Standby mode can be initiated at any time during readback; it is not necessary to retrieve all 18 bits of data beforehand. Figure 7. Data Retrieval with DRDY/DOUT Forced High Afterwards Figure 8. Standby Mode Timing (Can be used for single conversions) SYMBOL DESCRIPTION MIN TYP MAX UNITS SCLK high after DRDY/DOUT SPEED = 1 12.44 ms tDSS (1) goes low to activate Standby SPEED = 0 99.94 ms mode SPEED = 1 0.0125 s tSTANDBY Standby mode activation time SPEED = 0 0.1 s SPEED = 1 No change (typical time required) ms Data ready after exiting Standby tS_RDY (1) mode SPEED = 0 401.8 ms (1) Based on an ideal internal oscillator. Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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