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TPS92070PW Datasheet(PDF) 9 Page - Texas Instruments |
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TPS92070PW Datasheet(HTML) 9 Page - Texas Instruments |
9 / 20 page UDG-11187 VDD VZ 12.5 V BP SEN LP GATE PWM switching 0 V 0 V IOUT IMIN 7 V 0 V 0 V 6 V TPS92070 www.ti.com SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 APPLICATIONS STARTUP BIAS AND UVLO During powerup when VDD is less than the UVLO threshold of 8 V, the VZ pin is trickle charged with IVZ(start) of approximately 10 μA through the startup-resistor connected to the bulk rectified voltage. As VZ is being charged, VDD tracks VZ (less VGSTH) through the external cascode HV MOSFET (Q1) supplying a VDD startup current of 135 μA. Once VZ reaches the TPS92070 zener clamp regulation level of 12.5 V, the device enters into a stand-by mode during which the dimmer trigger circuit (DTC), set-point filter, 7-V bias regulator, and a minimal amount of housekeeping circuitry is active. The TPS92070 remains in this state until the SEN pin exceeds 5 V indicating that adequate line voltage is present, either through TRIAC firing, or line voltage presence. The typical start-up waveforms are shown in Figure 5. Figure 5. Typical Startup Waveforms for a TRIAC Triggered VIN(ac) Input Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :TPS92070 |
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