W25X16AVDAIZ datasheet(10/50 Pages) WINBOND

Part #	W25X16AVDAIZ

Description	16M-BIT, 32M-BIT, AND 64M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI

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Manufacturer	WINBOND [Winbond]

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W25X16, W25X16A, W25X32, W25X64

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11. FUNCTIONAL DESCRIPTION

11.1 SPI OPERATIONS

11.1.1 SPI Modes

The W25X16/16A/32/64 is accessed through an SPI compatible bus consisting of four signals: Serial

Clock (CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI

bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data

is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the

CLK signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of

the CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.

11.1.2 Dual Output SPI

The W25X16/16A/32/64 supports Dual output operation when using the "Fast Read with Dual Output"

(3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice

the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from

Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM

for execution. The Dual output feature simply allows the SPI input pin to also serve as an output

during this instruction. All other operations use the standard SPI interface with single output signal.

11.1.3 Hold Function

The /HOLD signal allows the W25X16/16A/32/64 operation to be paused while it is actively selected

(when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals

are shared with other devices. For example, consider if the page buffer was only partially written when

a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of

the instruction and the data in the buffer so programming can resume where it left off once the bus is

available again.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will

activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition

will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will terminate after the next falling edge of CLK.

During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data

Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept

active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the

device.

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