LPC4350_12 datasheet(81/149 Pages) PHILIPS

Part #	LPC4350

Description	32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals

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Manufacturer	PHILIPS [NXP Semiconductors]

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81 / 149 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 3.1 — 5 January 2012

81 of 149

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

• All I2C-bus controllers support multiple address recognition and a bus monitor mode.

7.18.6 I2S interface

Remark: The LPC4350/30/20/10 each contain two I2S-bus interfaces.

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S-bus connection has one master, which is

always the master, and one slave. The I2S-bus interface provides a separate transmit and

receive channel, each of which can operate as either a master or a slave.

7.18.6.1

Features

• Both I2S interfaces have separate input/output channels, each of which can operate in

master or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,

96, 192) kHz.

• Support for an audio master clock.

• Configurable word select period in master mode (separately for I2S-bus input and

output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests for each I2S interface, controlled by programmable buffer levels.

These are connected to the GPDMA block.

• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus

output.

7.18.7 C_CAN

Remark: The LPC4350/30/20/10 each contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of reliability.

7.18.7.1

Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

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LPC4350 Datasheet(PDF) 81 Page - NXP Semiconductors

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