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ICS8705 Datasheet(PDF) 11 Page - Integrated Device Technology |
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ICS8705 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 18 page 8705BY www.idt.com REV. H JULY 2, 2010 11 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FIGURE 3C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V R1 50 R3 50 Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input R2 50 Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V R3 125 R2 84 Zo = 50 Ohm 3.3V R4 125 LVPECL R1 84 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the V PP and VCMR input requirements. Figures 3A to 3D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are FIGURE 3A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another ven- dor, use their termination recommendation. 1.8V R2 50 Input LVHSTL Driver ICS HiPerClockS R1 50 LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm R1 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiv er CLK nCLK 3.3V |
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