Technical Note

4/19

BH6456GUL

www.rohm.com

2012.02 - Rev.A

© 2012 ROHM Co., Ltd. All rights reserved.

●

2 wire Serial Interface Register detail

●

Resister

Address W3 W2 W1 W0

D7

D6

D5

D4

D3

D2

D1

D0

0H

0

0

0

0

HiZE

initB[2]

initB[1]

InitB[0]

init

START

MODE

dir

1H

0

0

0

1

ta[7]

ta[6]

ta[5]

ta[4]

ta[3]

ta[2]

ta[1]

ta[0]

2H

0

0

1

0 brake1[7] brake1[6] brake1[5] brake1[4] brake1[3] brake1[2] brake1[1] brake1[0]

3H

0

0

1

1

tb[7]

tb[6]

tb[5]

tb[4]

tb[3]

tb[2]

tb[1]

tb[0]

4H

0

1

0

0 brake2[7] brake2[6] brake2[5] brake2[4] brake2[3] brake2[2] brake2[1] brake2[0]

5H

0

1

0

1

cnt[7]

cnt[6]

cnt[5]

cnt[4]

cnt[3]

cnt[2]

cnt[1]

cnt[0]

6H

0

1

1

0

cnt[15]

cnt[14]

cnt[13]

cnt[12]

cnt[11]

cnt[10]

cnt[9]

cnt[8]

7H

0

1

1

1

pa

pb

osc[2]

osc[1]

osc[0]

cntck[2]

cntck[1]

cntck[0]

8H

1

0

0

0

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

9H

1

0

0

1

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

AH

1

0

1

0

TEST

TEST

TEST

TEST

TEST

TEST

EXT

initEXT

BH

1

0

1

1

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

CH

1

1

0

0

TEST

TEST

TEST

TEST

TEST

TEST

TEST

TEST

Write mode : S

0

0

0

1

1

0

0

0

A PS T2 T1 T0 W3 W2 W1 W0 A D7D6D5 D4D3D2D1D0 A

P

Master is output

↑

↑

Write

Up date

Slave is output

Read mode : S

0

001

100

0

A PS T2 T1 T0 W3 W2 W1 W0 A

S

0

001

100

1

A D7 D6 D5 D4 D3 D2 D1 D0nA P

↑

↑

Write

Read

S=Start condition

A=Acknowledge

PS=Power save

W3～W0=Resister address

P=Stop condition

ｎA=not Acknowledge T2～T0=Test bit

D7～D0=Data