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AD5114BCPZ10-500R7 Datasheet(PDF) 9 Page - Analog Devices |
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AD5114BCPZ10-500R7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 28 page Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 9 of 28 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1 Test Conditions/ Comments Min Typ Max Unit Description fSCL2 Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t1 Standard mode 4.0 µs tHIGH, SCL high time Fast mode 0.6 µs t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CL 300 ns t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CL 300 ns t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 20 + 0.1 CL 300 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit. Fast mode 20 + 0.1 CL 300 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 20 + 0.1 CL 300 ns tSP3 Fast mode 0 50 ns Pulse width of suppressed spike tEEPROM_PROGRAM4 15 50 ms Memory program time tPOWER_UP5 50 µs Power-on EEPROM restore time tRESET 25 µs Reset EEPROM restore time 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 5 Maximum time after VDD is equal to 2.3 V. |
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