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AD9642-210EBZ Datasheet(PDF) 1 Page - Analog Devices |
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AD9642-210EBZ Datasheet(HTML) 1 Page - Analog Devices |
1 / 28 page 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9642 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. FEATURES SNR = 71.0 dBFS at 185 MHz AIN and 250 MSPS SFDR = 83 dBc at 185 MHz AIN and 250 MSPS −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS AIN, 250 MSPS Total power consumption: 390 mW at 250 MSPS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 350 MHz Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer Serial port control Energy saving power-down modes User-configurable, built-in self-test (BIST) capability APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications FUNCTIONAL BLOCK DIAGRAM 14 REFERENCE SERIAL PORT SCLK SDIO CSB CLK+ CLK– 1-TO-8 CLOCK DIVIDER AD9642 VIN+ D0±/D1± D12±/D13± DCO± VIN– VCM AVDD AGND DRVDD PARALLEL DDR LVDS AND DRIVERS PIPELINE 14-BIT ADC Figure 1. GENERAL DESCRIPTION The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The ADC output data is routed directly to the external 14-bit LVDS output port. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. 2. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. 3. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz. 4. 3-pin, 1.8 V SPI port for register programming and readback. 5. Pin compatibility with the AD9634, allowing a simple migra- tion from 14 bits to 12 bits, and with the AD6672. |
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