100 MHz to 4000 MHz

RF/IF Digitally Controlled VGA

Data Sheet

ADL5243

Rev. A

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FEATURES

Operating frequency from 100 MHz to 4000 MHz

Digitally controlled VGA with serial and parallel interfaces

6-bit, 0.5 dB digital step attenuator

31.5 dB gain control range with ±0.25 dB step accuracy

Gain Block Amplifier 1

Gain: 19.2 dB at 2140 MHz

OIP3: 40.2 dBm at 2140 MHz

P1dB: 19.8 dBm at 2140 MHz

Noise figure: 2.9 dB at 2140 MHz

¼ W Driver Amplifier 2

Gain: 14.2 dB at 2140 MHz

OIP3: 41.1 dBm at 2140 MHz

P1dB: 26.0 dBm at 2140 MHz

Noise figure: 3.7 dB at 2140 MHz

Gain block, DSA, or ¼ W driver amplifier can be first

Low quiescent current of 175 mA

The companion ADL5240 integrates a gain block with DSA

APPLICATIONS

Wireless infrastructure

Automated test equipment

RF/IF gain control

GENERAL DESCRIPTION

The ADL5243 is a high performance, digitally controlled

variable gain amplifier operating from 100 MHz to 4000 MHz.

The VGA integrates two high performance amplifiers and a

digital step attenuator (DSA). Amplifier 1 (AMP1) is an

internally matched gain block amplifier with 20 dB gain, and

Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier. The

DSA is 6-bit with a 31.5 dB gain control range, 0.5 dB steps, and

±0.25 dB step accuracy. The attenuation of the DSA can be

controlled using a serial or parallel interface.

The gain block and DSA are internally matched to 50 Ω at their

inputs and outputs, and all three internal devices are separately

biased. The separate bias allows all or part of the ADL5243 to be

used, which allows for easy reuse throughout a design. The

pinout of the ADL5243 also enables the gain block, DSA, or

¼ W driver amplifier to be first, giving the VGA maximum

flexibility in a signal chain.

The ADL5243 consumes 175 mA and operates off a single

supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a

thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully

specified for operation from −40°C to +85°C. A fully populated

evaluation board is available.

FUNCTIONAL BLOCK DIAGRAM

ADL5243

AMP1

9

10

11

12

13

14

15

16

SERIAL/PARALLEL INTERFACE

24

VDD

23

NC

22

NC

21

DSAOUT

20

NC

19

AMP2IN

18

NC

17

NC

0.5dB

1dB

2dB

4dB

8dB

16dB

32

31

30

29

28

27

26

25

1

VDD

2

NC

3

NC

4

DSAIN

5

NC

6

AMP1OUT/VCC

7

NC

8

NC

AMP2

Figure 1.