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HT46RU24 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT46RU24 Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 60 page  HT46RU24 Rev. 1.00 11 April 23, 2008 The I 2C Bus interrupt is initialized by setting the I2C Bus in- terrupt request flag (HIF; bit 5 of INTC1), caused by a slave address match (HAAS= ²1²) or one byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 14H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the ²RETI² in- struction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to en- able an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External Interrupt or A/D Conversion 1 04H Timer/Event Counter 0 Overflow 2 08H Timer/Event Counter 1 Overflow 3 0CH UART Bus Interrupt 4 10H I 2C Bus Interrupt 5 14H Timer/Event Counter 2 Overflow 6 18H The Timer/Event Counter 0/1/2 interrupt request flag (T0F, T1F, T2F), external interrupt request flag (EIF), A/D converter request flag (ADF), the I 2C Bus interrupt request flag (HIF), UART Bus interrupt request flag (URF), enable timer/event counter bit (ET0I, ET1I, ET2I), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI), enable I 2C Bus interrupt bit (EHI), enable UART interrupt bit (EURI) and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) and an interrupt control register 1 (INTC1) which are located at 0BH and 1EH in the data memory. EMI, EEI, ET0I, ET1I, ET2I, EADI, EHI, EURI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F, T2F, EIF, ADF, HIF, URF) are set, they will remain in the INTC0 and INTC1 register until the interrupts are ser- viced or cleared by a software instruction. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well con- trolled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller. Both are designed for system clocks, namely the RC os- cillator and the Crystal oscillator, which are determined by the option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external sig- nal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 24k W to 1MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC os- cillator provides the most cost effective solution. How- ever, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process varia- tions. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resona- tor can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating fre- quency is less than 1MHz). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the sys- tem enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65 ms at 5V. The WDT oscillator can be dis- abled by option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (sys- tem clock divided by 4) decided by options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable re- sults. The watchdog timer can be disabled by a option. If the watchdog timer is disabled, all the executions re- lated to the WDT result in no operation. Once an internal WDT oscillator (RC oscillator with pe- riod 65 ms at 5V normally) is selected, it is divided by C r y s t a l O s c i l l a t o r R C O s c i l l a t o r O S C 1 O S C 2 O S C 2 f S Y S / 4 O S C 1 V D D 4 7 0 p F System Oscillator |
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