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TLE42764GV Datasheet(PDF) 5 Page - Infineon Technologies AG |
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TLE42764GV Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 20 page TLE42764 Pin Configuration Data Sheet 5 Rev. 1.2, 2011-02-15 3.3 Pin Assignment PG-SSOP-14 exposed pad Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-SSOP-14 exposed pad Pin No. Symbol Function 1, 3, 5-7 n.c. non connected can be open or connected to GND 2EN Enable Input high level input signal enables the IC; low level input signal disables the IC; integrated pull-down resistor 4GND Ground 8, 10-12, 14 n.c. non connected can be open or connected to GND 9Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 7 13 I Input block to ground directly at the IC with a ceramic capacitor Exposed Pad – Exposed Pad connect to GND and heatsink area n.c. n.c. Q n.c. n.c. n.c. I n.c. n.c. n.c. n.c. GND n.c. EN 1 2 3 4 5 6 7 14 9 10 11 12 13 8 PINCONFIG_SSOP-14.SVG |
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