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TPS84610 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS84610 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 27 page PWRGD VIN PGND PH VOUT RT/CLK VADJ STSEL SS/TR VSENSE+ TPS84610 PWRGD Logic + + VREF Comp Power Stage and Control Logic Thermal Shutdown Shutdown Logic VIN UVLO OSC w/PLL INH/UVLO AGND OCP TPS84610 www.ti.com SLVSAZ4 – OCTOBER 2011 ELECTRICAL CHARACTERISTICS (continued) Over -40 °C to 85°C free-air temperature, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 6A, CIN1 = 47 µF ceramic, CIN2 = 220 µF poly-tantalum, COUT1 = 47 µF ceramic, COUT2 = 100 µF poly-tantalum (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ceramic 47 (5) CIN External input capacitance µF Non-ceramic 220(5) Ceramic 47 (6) 150 650(7) µF COUT External output capacitance Non-ceramic 100(6) 2000(7) Equivalent series resistance (ESR) 25 m Ω (5) A minimum of 47 µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor close to the device. An additional 220 µF of bulk capacitance is recommended. See Table 4 for more details. (6) The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance must include at least 47 µF of ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 4 for more details. (7) When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 2200 µF. DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS84610 |
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