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DS1746P-70IND+ Datasheet(PDF) 3 Page - Maxim Integrated Products |
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DS1746P-70IND+ Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 16 page DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs 3 of 16 ORDERING INFORMATION PART VOLTAGE RANGE (V) TEMP RANGE PIN-PACKAGE TOP MARK† DS1746-70+ 5.0 0°C to +70°C 32 EDIP (0.740a) DS1746+070 DS1746-70IND+ 5.0 -40°C to +85°C 32 EDIP (0.740a) DS1746+070 IND DS1746P-70+ 5.0 0°C to +70°C 34 PowerCap* DS1746P+70 DS1746P-70IND+ 5.0 -40°C to +85°C 34 PowerCap* DS1746P+070 IND DS1746W-120+ 3.3 0°C to +70°C 32 EDIP (0.740a) DS1746W+120 DS1746W-120IND+ 3.3 -40°C to +85°C 32 EDIP (0.740a) DS1746W+120 IND DS1746WP-120+ 3.3 0°C to +70°C 34 PowerCap* DS1746WP+120 DS1746WP-120IND+ 3.3 -40°C to +85°C 34 PowerCap* DS1746WP+120 IND +Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately). † An “IND” anywhere on the top mark denotes an industrial temperature grade device. DESCRIPTION The DS1746 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 128k x 8 nonvolatile static RAM. User access to all registers within the DS1746 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1746 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. |
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