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S10141-1107S Datasheet(PDF) 10 Page - Hamamatsu Corporation |
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S10141-1107S Datasheet(HTML) 10 Page - Hamamatsu Corporation |
10 / 13 page CCD area image sensor S10140/S10141 series 10 Speci cations of built-in TE-cooler (Typ.) Pin connections Parameter Symbol Condition S10141-1007S/-1008S/-1009S S10141-1107S/-1108S/-1109S Unit Internal resistance Rint Ta=25 °C 2.5 1.2 Maximum current*19 Imax Tc*20=Th*21=25 °C 1.5 3.0 A Maximum voltage Vmax Tc*20=Th*21=25 °C 3.8 3.6 V Maximum heat absorption*21 Qmax 3.4 5.1 W Maximum temperature of heat radiating side -70 70 °C * 19: If the current greater than this value ows into the thermoelectric cooler, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60 % of this maximum current. * 20: Temperature of the cooling side of thermoelectric cooler. * 21: Temperature of the heat radiating side of thermoelectric cooler. * 22: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit. Pin No. S10140 series S10141 series Remark (standard operation) Symbol Function Symbol Function 1 RD Reset drain RD Reset drain +12 V 2 OS Output transistor source OS Output transistor source RL=100 k 3 OD Output transistor drain OD Output transistor drain +24 V 4 OG Output gate OG Output gate +3 V 5 SG Summing gate SG Summing gate Same pulse as P2H 6- - 7- - 8 P2H CCD horizontal register clock-2 P2H CCD horizontal register clock-2 9 P1H CCD horizontal register clock-1 P1H CCD horizontal register clock-1 10 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2) -8 V 11 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1) -8 V 12 ISH Test point (horizontal input source) ISH Test point (horizontal input source) Connect to RD 13 TG*18 Transfer gate TG*18 Transfer gate Same pulse as P2V 14 P2V CCD vertical register clock-2 P2V CCD vertical register clock-2 15 P1V CCD vertical register clock-1 P1V CCD vertical register clock-1 16 - Th1 Thermistor 17 - Th2 Thermistor 18 - P- TE-cooler- 19 - P+ TE-cooler+ 20 SS Substrate (GND) SS Substrate (GND) GND 21 ISV Test point (vertical input source) ISV Test point (vertical input source) Connect to RD 22 IG2V Test point (vertical input gate-2) IG2V Test point (vertical input gate-2) -8 V 23 IG1V Test point (vertical input gate-1) IG1V Test point (vertical input gate-1) -8 V 24 RG Reset gate RG Reset gate * 18: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as P2V. |
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