MAX1257 datasheet(7/43 Pages) MAXIM

Part #	MAX1257

Description	12-Bit, Multichannel ADCs/DACs with FIFO,Temperature Sensing, and GPIO Ports

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Manufacturer	MAXIM [Maxim Integrated Products]

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12-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

_______________________________________________________________________________________

7

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD

(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,

unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.

Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (Figures 6–13)

SCLK Clock Period

tCP

40

ns

SCLK Pulse-Width High

tCH

40/60 duty cycle

16

ns

SCLK Pulse-Width Low

tCL

60/40 duty cycle

16

ns

GPIO Output Rise/Fall After

CS Rise

tGOD

CLOAD = 20pF

100

ns

GPIO Input Setup Before CS

Fall

tGSU

0

ns

LDAC Pulse Width

tLDACPWL

20

ns

CLOAD = 20pF, SLOW = 0

1.8

12.0

SCLK Fall to DOUT Transition

(Note 16)

tDOT

CLOAD = 20pF, SLOW = 1

10

40

ns

CLOAD = 20pF, SLOW = 0

1.8

12.0

SCLK Rise to DOUT Transition

(Notes 16, 17)

tDOT

CLOAD = 20pF, SLOW = 1

10

40

ns

CS Fall to SCLK Fall Setup Time

tCSS

10

ns

SCLK Fall to CS Rise Hold Time

tCSH

0

2000

ns

DIN to SCLK Fall Setup Time

tDS

10

ns

DIN to SCLK Fall Hold Time

tDH

0

ns

CS Pulse-Width High

tCSPWH

50

ns

CS Rise to DOUT Disable

tDOD

CLOAD = 20pF

25

ns

CS Fall to DOUT Enable

tDOE

CLOAD = 20pF

1.5

25.0

ns

EOC Fall to CS Fall

tRDS

30

ns

CKSEL = 01 (temp sense) or CKSEL =

10 (temp sense), internal reference on

(Note 18)

65

CKSEL = 01 (temp sense) or CKSEL =

10 (temp sense), internal reference

initially off

140

CKSEL = 01 (voltage conversion)

9

CKSEL = 10 (voltage conversion),

internal reference on (Note 18)

9

CS or CNVST Rise to EOC

Fall—Internally Clocked

Conversion Time

tDOV

CKSEL = 10 (voltage conversion),

internal reference initially off

80

µs

CKSEL = 00, CKSEL = 01 (temp sense)

40

ns

CNVST Pulse Width

tCSW

CKSEL = 01 (voltage conversion)

1.4

µs

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