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AKD4122A Datasheet(PDF) 11 Page - Asahi Kasei Microsystems

Part # AKD4122A
Description  24-Bit 96kHz SRC with DIR
Download  54 Pages
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AKD4122A Datasheet(HTML) 11 Page - Asahi Kasei Microsystems

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[AK4122A]
MS1076-E-01
2010/05
- 11 -
Parameter
Symbol
min
typ
max
Units
Output for PORT3 (Slave mode)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑”
(Note 11)
BICK “
↑” to LRCK Edge
(Note 11)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “
↓” to SDTO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Output for PORT2 (Master mode)
BICK2 Frequency
BICK2 Duty
BICK2 “
↓” to LRCK2
BICK2 “
↓” to SDTIO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
30
Hz
%
ns
ns
Output for PORT3 (Master mode)
BICK Frequency
BICK Duty
BICK “
↓” to LRCK
BICK “
↓” to SDTO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
30
Hz
%
ns
ns
Control Interface Timing
CCLK Period
(Note 12)
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
↓” to CCLK “↑”
CCLK “
↑” to CSN “↑”
CDTO Delay
CSN “
↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
1000
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width
(Note 13)
tPD
150
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. In case of using INT2. When INT2 is not used, the max value is not limited.
Note 13. The AK4122A can be reset by bringing the PDN pin = “L”.


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