[AK4340]

MS0501-E-01

2010/09

- 11 -

MCLK

Sampling Speed

1152fs

Normal (fs=32kHz Only)

512fs

768fs

Normal

256fs

384fs

Double

128fs

192fs

Quad

Table 3. Sampling Speed (Auto Setting Mode: Default at Serial control mode)

LRCK

MCLK (MHz)

fs

128fs

192fs

256fs

384fs

512fs

768fs

1152fs

Sampling

Speed

32.0kHz

-

-

-

-

16.3840

24.5760

36.8640

44.1kHz

-

-

-

-

22.5792

33.8688

-

48.0kHz

-

-

-

-

24.5760

36.8640

-

Normal

88.2kHz

-

-

22.5792

33.8688

-

-

-

96.0kHz

-

-

24.5760

36.8640

-

-

-

Double

176.4kHz

22.5792

33.8688

-

-

-

-

-

192.0kHz

24.5760

36.8640

-

-

-

-

-

Quad

Table 4. System Clock Example (Auto Setting Mode)

Data is shifted in via the SDTI pin using BICK and LRCK inputs. In serial control mode, five serial data mode can be

selected by DIF2-0 bits. (See Table 5). In parallel control mode, two serial data mode can be selected by DIF0 pin. (See

Table 6) In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode

2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.

Mode

DIF2

DIF1

DIF0

SDTI Format

BICK

Figure

0

0

0

0

16bit LSB Justified

≥32fs

Figure 6

1

0

0

1

20bit LSB Justified

≥40fs

Figure 7

2

0

1

0

24bit MSB Justified

≥48fs

Figure 8

Default

3

0

1

1

24bit I

≥48fs

Figure 9

4

1

0

0

24bit LSB Justified

≥48fs

Figure 7

Table 5. Audio Data Format in Serial control mode

Mode

DIF0

SDTI Format

BICK

Figure

2

0

24bit MSB Justified

≥48fs

Figure 8

3

1

24bit I

≥48fs

Figure 9

Table 6. Audio Data Format in Parallel control mode