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AK4424 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4424 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 19 page ![]() [AK4424] MS0935-E-03 2010/09 - 10 - LRCK BICK (64fs) SDTI 0 3 1 2 24 31 0 1 31 0 1 23:MSB, 0:LSB 22 1 0 Don’t care 23 Lch Data Rch Data 23 25 3 224 23 25 22 1 0 Don’t care 23 23 Figure 3. Audio Interface Timing De-emphasis Filter The AK4424 integrates digital de-emphasis filter (tc = 50/15µs). The DEM pin which enables the digital de-emphasis filter by setting “H” is internal pull-down pin. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain error when the de-emphasis filter is enabled. In case of double speed mode (MCLK=256fs/384fs) and quad speed mode (MCLK=128fs/192fs), the digital de-emphasis filter is always off. DEM pin De-emphasis Filter 1 ON 0 OFF (default) Table 4. De-emphasis Filter Control (Normal Speed Mode) ■ Zero detect function When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. If the input data of Lch and Rch are continuously not zeros orderly, or if each Rch or Lch is continuously not zeros, the DZF pin immediately returns to “L”. |
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