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AK4424 Datasheet(PDF) 13 Page - Asahi Kasei Microsystems

Part No. AK4424
Description  192kHz 24-Bit Stereo ?誇 DAC with 2Vrms Output
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK4424 Datasheet(HTML) 13 Page - Asahi Kasei Microsystems

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[AK4424]
MS0935-E-03
2010/09
- 13 -
System Reset
The AK4424 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4424 is in power-down mode until LRCK are input.
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8) : Double speed mode
Time A = 1024/ (fs x 4) : Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different timing from this figure.
Figure 7. System reset diagram
D/A Out
(Analog)
MCLK
DZF
20 us
Low
Power Supply
(VDD, CVDD)
2, 3
LRCK
Digital
Circuit
Analog
Circuit
Charge Pump
Circuit
Charge Pump
Counter circuit
Time A
(1)
(2)
(3)
(5)
Power-up
Power-up
“0” data
D/A In
(Digital)
MUTE (D/A Out)
(4)
(6)
Power down
Power down
Power-up
Power down


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