[AK4687]

MS1307-E-00

2011/05

- 9 -

DC CHARACTERISTICS

(Ta= 25

°C; AVDD1=AVDD2= DVDD= 3.3V)

Parameter

Symbol

min

typ

max

Units

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

70%DVDD

-

-

-

-

30%DVDD

V

V

High-Level Output Voltage (Iout=-400

μA)

Low-Level Output Voltage

(Iout= -400

μA(except SDA pin), 3mA(SDA pin))

VOH

VOL

DVDD-0.4

-

-

-

0.4

V

V

Input Leakage Current

Iin

-

-

±10

μA

SWITCHING CHARACTERISTICS

(Ta=25

Parameter

Symbol

min

typ

max

Units

Master Clock Timing

Frequency

Duty

fECLK

dECLK

8.192

40

50

36.864

60

MHz

%

Master Clock

256fsn, 128fsd:

Pulse Width Low

Pulse Width High

384fsn, 192fsd:

Pulse Width Low

Pulse Width High

512fsn, 256fsd, 128fsq:

Pulse Width Low

Pulse Width High

768fsn, 384fsd, 192fsq:

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

8.192

0.37

0.37

12.288

0.37

0.37

16.384

0.37

0.37

24.576

0.37

0.37

12.288

18.432

24.576

36.864

MHz

1/fCLK

1/fCLK

MHz

1/fCLK

1/fCLK

MHz

1/fCLK

1/fCLK

MHz

1/fCLK

1/fCLK

LRCK1Timing (Slave Mode)

Duty Cycle

fsn

Duty

32

45

48

55

kHz

%

LRCK2Timing (Slave Mode)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

Duty Cycle

fsn

fsd

fsq

Duty

32

32

128

45

48

96

192

55

kHz

kHz

kHz

%

LRCK1 Timing (Master Mode)

Normal Speed Mode

Duty Cycle

fsn

Duty

32

50

48

kHz

%

Power-down & Reset Timing

PDN Pulse Width

(Note 11)

PDN “

↑” to SDTO valid

(Note 12)

tPD

tPDV

150

2640

ns

1/fs

Note 11. Refer to the “■ System Reset” paragraph for the reset by PDN1 and PDN2 pins.

Note 12. After a rising edge of PDN1, the internal counter starts by divided clock of MCLK and ADC power down is

released by a falling edge of CVEE after 64/fs on LRCK, then SDTIO is output 528/fs later.