[AK7719]

MS1351-E-00-PB

2012/01

8

(Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V) CL=20pF (except SDA pin) or 400pF (SDA pin);

unless otherwise specified

Parameter

Symbol

min

typ

max

Unit

Normal Operation mode: SYNC1/3, BCLK1/BCLK3 Input Timing

SYNC1/3 Input Timing

SYNC1/3 frequency

fs

8

48

kHz

BCLK1 Input Timing (Note 8, Note 9)

fBCLK

64

3072

kHz

BCLK1/3 Pulse width Low

tBCKL

0.4 x tBCLK

ns

BCLK1/3 Pulse width High

tBCKH

0.4x tBCLK

ns

Note 8. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be stable

Note 9. Required fBCLK: ≥ 2 (Data length set by LAW bit) x SYNC2 frequency

(Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V)

Parameter

Symbol

min

typ

max

Unit

PDN

(Note 10)

tPDN

600

ns

Note 10. The AK7719 can be reset by bringing the PDN pin = “L” upon power-up.

(Ta= -20ºC ~ 85ºC, TVDD= 1.6V ~ 3.6V, VSS=0V, CL=20pF)

Parameter

Symbols

min

typ

max

Unit

SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4

Delay Time from BCLK1 “↑” to SYNC1 “↑”

(Note 11)

tBSYD

20

ns

Delay Time from SYNC1 “↓” to BCLK1 “↑”

tSYBD

100

ns

Serial Data Input Latch Setup Time

tB1IDS

40

ns

Serial Data Input Latch Hold Time

tB1IDH

40

ns

Delay Time from SYNC1 to Serial Data Output

tSY1OD

40

ns

Delay Time from BCLK1 “↓” to Serial Data Output (Note 12)

tB1OD

40

ns

SDIN2, SDOUT2

SYNC2 Duty cycle

50

%

Serial Data Input Latch Setup Time

tB2IDS

40

ns

Serial Data Input Latch Hold Time

tB2IDH

40

ns

Delay Time from SYNC2 to Serial Data Outputs

tSY2OD

40

ns

Delay Time from BCLK2 “↓”to Serial Data Output (Note 13)

tB2OD

40

ns

SDINn → SDOUTn (n=1, 2, 3)

Delay time from SDINn to SDOUTn Output

tIOD

60

ns

Note 11. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “

↓”

Note 12. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↑”.

Note 13. When the polarity of BCLK2 is inverted, delay time is from BCLK2 “↑”.

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