AK8130

MS0598-E-03

Feb-08

- 5 -

The brand name

of AKEMD’s IC’s

Output clock frequency selection

The AK8130 generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs and

provides to up to four assigned outputs. A frequency selection at assigned output pin is configured by

pin-setting of S0 (Pin2), S1 (Pin3), and S2 (Pin14).

The selectable frequency is shown in Table 1..

Table 1: Clock output Frequency

Selection Pin

Clock Output Frequency (MHz)

S2

(Pin 14)

S1

(Pin 3)

S0

(Pin 2)

CLK1

(Pin 7)

CLK2

(Pin 8)

CLK3

(Pin 10)

CLK4

(Pin 11)

L

L

L

74.250

25.000

OFF

33.333

L

L

H

74.250

25.000

4.9152

OFF

L

H

L

74.250

25.000

OFF

24.576

L

H

H

54.000

OFF

4.9152

24.576

H

L

L

74.1758

25.000

OFF

33.333

H

L

H

74.1758

25.000

4.9152

OFF

H

H

L

74.1758

25.000

OFF

24.576

H

H

H

74.1758

OFF

4.9152

24.576

Voltage Control Crystal Oscillator (VCXO)

The AK8130 has a voltage control crystal oscillator (VCXO), featuring fine frequency tuning for 27MHz of

primary clock frequency by external DC voltage control.

This tuning enables output clock frequency to

synchronize the external clock system.

VIN (Pin 4) accepts DC voltage control from a processor or a

system controller, and pulls the primary frequency of crystal to higher or lower.

This pulling range is

determined by crystal characteristic, on-chip load capacitor, and stray capacitance of PCB.

The AK8130

is designed to range

±110ppm of primary frequency in AKEMD’s authorized condition, and the typical

pulling profile is shown in Figure 1.

For details about the condition and other specific crystal application

case, refer the AK8130 Family application note.

27.0MHz VCXO Characteristics NDK AT-41CD2（CL=12.0pF）

（Cext1=18.0pF,Cext2=5.0pF)

-150

-100

-50

0

50

100

150

0

0.5

1

1.5

2

2.5

3

3.5

VIN(V)

Figure 1: Typical VCXO Pulling Profile