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BS616UV2019DCG85 Datasheet(PDF) 8 Page - Brilliance Semiconductor

Part # BS616UV2019DCG85
Description  Ultra Low Power CMOS SRAM 128K X 16 bit
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Manufacturer  BSI [Brilliance Semiconductor]
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BS616UV2019DCG85 Datasheet(HTML) 8 Page - Brilliance Semiconductor

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BS616UV2019
R0201-BS616UV2019
Revision
1.4
Oct.
2008
8
WRITE CYCLE 2
(1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE going low or CE2 going high to the end of write.
12.48B BGA ignore this parameters related to CE2.
tWC
tCW
(11)
tWP
(2)
tAW
tWHZ
(4,10)
tAS
tWR
(3)
tDH
tDW
DIN
DOUT
WE
LB, UB
CE
ADDRESS
(5)
tOW
(7)
(8)
(8,9)
tBW
(5)
CE2
(5,12)


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