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SCM6323AYJ12AR Datasheet(PDF) 8 Page - Motorola, Inc |
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SCM6323AYJ12AR Datasheet(HTML) 8 Page - Motorola, Inc |
8 / 12 page MCM6323A 8 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) P Sb l MCM6323A–10 MCM6323A–12 MCM6323A–15 Ui N Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 10 — 12 — 15 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 8 — 9 — 10 — ns Enable to End of Write tELEH, tELWH 8 — 9 — 10 — ns 4, 5 Data Valid to End of Write tDVEH 4 — 5 — 6 — ns Data Hold Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low, W low, and LB and/or UB low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 (E Controlled) tEHDX tDVEH tEHAX tELWH tELEH tAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) LB, UB (BYTE ENABLE) |
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