DMOS Microstepping Driver with Translator

And Overcurrent Protection

A4982

9

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

comparator in precise steps, such that

It is critical that the maximum rating (0.5 V) on the SENSE1 and

SENSE2 pins is not exceeded.

uses a one-shot circuit to control the duration of time that the

ROSC terminal. The ROSC terminal has three settings:

▪ ROSC tied to VDD — off-time internally set to 30 μs, decay

mode is automatic Mixed decay except when in full step where

decay mode is set to Slow decay

▪ ROSC tied directly to ground — off-time internally set to

30 μs, current decay is set to Mixed decay for both increasing

and decreasing currents, except in full step where decay mode

is set to Slow decay. (See Low Current Microstepping section.)

▪ ROSC through a resistor to ground — off-time is determined

by the following formula , the decay mode is automatic Mixed

decay for all step modes.

comparators when the outputs are switched by the internal current

control circuitry. The comparator outputs are blanked to prevent

false overcurrent detection due to reverse recovery currents of the

clamp diodes, and switching transients related to the capacitance

Shorted-Load and Short-to-Ground Protection.

If the motor leads are shorted together, or if one of the leads is

shorted to ground, the driver will protect itself by sensing the

overcurrent event and disabling the driver that is shorted, protect-

ing the device from damage. In the case of a short-to-ground, the

device will remain disabled (latched) until the S¯¯L¯¯E¯¯E¯¯P¯ input goes

high or VDD power is removed. A short-to-ground overcurrent

event is shown in figure 4.

When the two outputs are shorted together, the current path is

through the sense resistor. After the blanking time (

≈1 μs) expires,

the sense resistor voltage is exceeding its trip value, due to the

overcurrent condition that exists. This causes the driver to go into

a fixed off-time cycle. After the fixed off-time expires the driver

turns on again and the process repeats. In this condition the driver

is completely protected against overcurrent events, but the short

is repetitive with a period equal to the fixed off-time of the driver.

This condition is shown in figure 5.

If the driver is operating in Mixed decay mode, it is normal for

the positive current to spike, due to the bridge going in the for-

ward direction and then in the negative direction, as a result of the

direction change implemented by the Mixed decay feature. This

is shown in figure 6. In both instances the overcurrent circuitry is

protecting the driver and prevents damage to the device.

generate a gate supply greater than that of VBB for driving the

source-side FET gates. A 0.1 μF ceramic capacitor, should be

connected between CP1 and CP2. In addition, a 0.1 μF ceramic

capacitor is required between VCP and VBB, to act as a reservoir

for operating the high-side FET gates.

Capacitor values should be Class 2 dielectric ±15% maximum,

or tolerance R, according to EIA (Electronic Industries Alliance)

specifications.

operate the sink-side FET outputs. The nominal output voltage

of the VREG terminal is 7 V. The VREG pin must be decoupled

monitored. In the case of a fault condition, the FET outputs of the

A4982 are disabled.

Capacitor values should be Class 2 dielectric ±15% maximum,

or tolerance R, according to EIA (Electronic Industries Alliance)

specifications.

FET outputs. When set to a logic high, the outputs are disabled.

When set to a logic low, the internal control enables the outputs as

required. The translator inputs STEP, DIR, MS1, and MS2, as well

as the internal sequencing logic, all remain active, independent of

the ¯E¯¯N¯¯A¯¯B¯¯L¯¯E¯ input state.

or an undervoltage (on VCP), the FET outputs of the A4982 are

disabled until the fault condition is removed. At power-on, the

UVLO (undervoltage lockout) circuit disables the FET outputs

and resets the translator to the Home state.