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ADF4196BCPZ-RL7 Datasheet(PDF) 7 Page - Analog Devices |
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ADF4196BCPZ-RL7 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 28 page  Data Sheet ADF4196 Rev. B | Page 7 of 28 Pin No. Mnemonic Description 23 RSET Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is SET CP R I 25 . 0 = Therefore, with RSET = 2.4 kΩ, ICP = 104 µA. 24 VP2 Power Supply Pin for the Charge Pump. Nominally 5 V, VP2 should be at the same voltage as VP1. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. 25 AIN− Negative Input Pin for the Differential Amplifier. 26 CPOUT− Differential Charge Pump Negative Output Pin. Connect this pin to AIN− and the loop filter. 27 SW2 Fast Lock Switch 2. This switch is closed to SWGND when the SW1/SW2 timeout counter is active. 28 SWGND Ground for SW1 and SW2 Switches. Connect this pin to the ground plane. 29 SW1 Fast Lock Switch 1. This switch is closed to SWGND when the SW1/SW2 timeout counter is active. 30 CPOUT+ Differential Charge Pump Positive Output Pin. Connect this pin to AIN+ and the loop filter. 31 AIN+ Positive Input Pin for the Differential Amplifier. 32 VP3 Power Supply Pin for the Differential Amplifier. Ranges from 5.0 V to 5.5 V. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. VP3 also requires a 10 µF decoupling capacitor to the ground plane. EP Exposed Paddle. The exposed paddle must be connected to the ground plane. |
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