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ADIS16480AMLZ Datasheet(PDF) 24 Page - Analog Devices

Part No. ADIS16480AMLZ
Description  Ten Degrees of Freedom Inertial Sensor
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16480AMLZ Datasheet(HTML) 24 Page - Analog Devices

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ADIS16480
Data Sheet
Rev. 0 | Page 24 of 40
DIGITAL SIGNAL PROCESSING
GYROSCOPES/ACCELEROMETERS
Figure 20 provides a block diagram for all of the components
and settings that influence the frequency response for the
accelerometers and gyroscopes. The sample rate for each
accelerometer and gyroscope is 9.84 kHz. Each sensor has
its own averaging/decimation filter stage, which reduces the
update rate to 2.46 kSPS. When using the external clock option
(FNCTIO_CTRL[7:4], see Table 149), the input clock drives a
4-sample burst at a sample rate of 9.84 kSPS, which feeds into
the 4× averaging/decimation filter. This results in a data rate
that is equal to the input clock frequency. Note that the
sensitivity to coning and sculling depends on the sample
rate. At 2.46 kHz, the sensitivity is very low, but can become
influential at lower sample rates. For best performance when
using an external clock, use the maximum input frequency
of 2.4 kHz.
AVERAGING/DECIMATION FILTER
The DEC_RATE register (see Table 67) provides user control
for the final filter stage (see Figure 20), which averages and
decimates the accelerometers, gyroscopes, delta angle, and delta
velocity data. Note that the orientation outputs do not go through
an averaging stage, prior to decimation. The output sample rate is
equal to 2460/(DEC_RATE + 1). When using the external clock
option (FNCTIO_CTRL[7:4], see Table 149), replace the 2460
number in this relationship, with the input clock frequency. For
example, turn to Page 3 (DIN = 0x8003), and set DEC_RATE =
0x18 (DIN = 0x8C18, then DIN = 0x8D00) to reduce the output
sample rate to 98.4 SPS (2460 ÷ 25).
Table 67. DEC_RATE (Page 3, Base Address = 0x0C)
Bits
Description (Default = 0x0000)
[15:11]
Don’t care
[10:0]
Decimation rate, binary format, maximum = 2047
See Figure 20 for impact on sample rate
MAGNETOMETER/BAROMETER
When using the internal sampling clock, the magnetometer
output registers (xMAGN_OUT) update at a rate of 102.5 SPS
and the barometer output registers (BAROM_xxx) update at a
rate of 51.25 SPS. When using the external clock, the magne-
tometers update at a rate of 1/24th of the input clock frequency
and the barometers update at a rate that is 1/48th of the input
clock frequency. The update rates for the magnetometer and
barometers do not change with the DEC_RATE register
settings. SYS_E_FLAG[9:8] (see Table 59) offer new data bits
for these registers and the SEQ_CNT register provides a counter
function to help determine when there is new data in the
magnetometer and barometer registers. When SEQ_CNT =
0x0001, there is new data in the magnetometer and barometer
output registers. The SEQ_CNT register can be useful during
initialization to help synchronize read loops for new data in
both magnetometer and barometer outputs. When beginning a
continuous read loop, read SEQ_CNT, then subtract this value
from the maximum value shown (range) in Table 68 to calculate
the number of internal sample cycles until both magnetometer
and barometer data is new.
Table 68. SEQ_CNT (Page 0, Base Address = 0x06)
Bits
Description
[15:11]
Don’t care
[6:0]
Binary counter: range = 1 to 48/(DEC_RATE + 1)
MEMS
SENSOR
330Hz
÷4
2.46kHz, fs
GYROSCOPE
2-POLE: 404Hz, 757Hz
ACCELEROMETER
1-POLE: 330Hz
AVERAGE
DECIMATION
FILTER
1
4
4
fs
INTERNAL
CLOCK
9.84kHz
DIOx
OPTIONAL INPUT CLOCK
FNCTIO_CTRL[7] = 1
fs < 2400Hz
NOTES
1. WHEN FNCTIO_CTRL[7] = 1, EACH CLOCK PULSE ON THE DESIGNATED DIOx LINE (FNCTIO_CTRL[5:4]) STARTS A 4-SAMPLE BURST,
AT A SAMPLE RATE OF 9.84kHz. THESE FOUR SAMPLES FEED INTO THE 4x AVERAGE/DECIMATION FILTER, WHICH PRODUCES A
DATA RATE THAT IS EQUAL TO THE INPUT CLOCK FREQUENCY.
ORIENTATION
÷D
÷D
1
D
D
FIR
EKF
FILTER
BANK
AVERAGE/DECIMATION
FILTER
D = DEC_RATE[10:0] + 1
SELECTABLE
FIR FILTER BANK
FILTR_BNK_0
FILTR_BNK_1
Figure 20. Sampling and Frequency Response Block Diagram


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