Rev. B | Page 9 of 36
The ADIS16488 is an autonomous sensor system that starts up
on its own when it has a valid power supply. After running through
its initialization process, it begins sampling, processing, and
loading calibrated sensor data into the output registers, which
are accessible using the SPI port. The SPI port typically connects to
a compatible port on an embedded processor, using the connection
diagram in Figure 11. The four SPI signals facilitate synchronous,
serial data communication. Connect RST (see Table 5) to VDD
or leave it open for normal operation. The factory default
configuration provides users with a data-ready signal on the
DIO2 pin, which pulses high when new data is available in the
output data registers.
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
Figure 11. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Master output, slave input
Master input, slave output
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices
such as the ADIS16488. Table 7 provides a list of settings, which
describe the SPI protocol of the ADIS16488. The initialization
routine of the master processor typically establishes these settings
using firmware commands to write them into its serial control
Table 7. Generic Master Processor SPI Settings
The ADIS16488 operates as a slave.
SCLK ≤ 15 MHz
Maximum serial clock rate.
SPI Mode 3
CPOL = 1 (polarity), and CPHA = 1 (phase).
Shift register/data length.
The register structure and SPI port provide a bridge between
the sensor processing system and an external, master processor.
It contains both output data and control registers. The output
data registers include the latest sensor data, a real-time clock, error
flags, alarm flags, and identification data. The control registers
include sample rate, filtering, input/output, alarms, calibration,
and diagnostic configuration options. All communication
between the ADIS16488 and an external processor involves
either reading or writing to one of the user registers.
Figure 12. Basic Operation
The register structure uses a paged addressing scheme that is
composed of 13 pages, with each one containing 64 register
locations. Each register is 16 bits wide, with each byte having its
own unique address within that page’s memory map. The SPI
port has access to one page at a time, using the bit sequence in
Figure 17. Select the page to activate for SPI access by writing its
code to the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Table 8 displays the
PAGE_ID contents for each page, along with their basic functions.
The PAGE_ID register is located at Address 0x00 on every page.
Table 8. User Register Page Assignments
Output data, clock, identification
Control: sample rate, filtering, I/O, alarms
FIR Filter Bank A Coefficient 0 to Coefficient 59
FIR Filter Bank A, Coefficient 60 to Coefficient 119
FIR Filter Bank B, Coefficient 0 to Coefficient 59
FIR Filter Bank B, Coefficient 60 to Coefficient 119
FIR Filter Bank C, Coefficient 0 to Coefficient 59
FIR Filter Bank C, Coefficient 60 to Coefficient 119
FIR Filter Bank D, Coefficient 0 to Coefficient 59
FIR Filter Bank D, Coefficient 60 to Coefficient 119