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ADM1075-1ACPZ Datasheet(PDF) 25 Page - Analog Devices |
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ADM1075-1ACPZ Datasheet(HTML) 25 Page - Analog Devices |
25 / 52 page Data Sheet ADM1075 Rev. A | Page 25 of 52 the voltage connected to the UVL pin falls below 0.9 V, and the gate is shut down using the 10 mA pull-down device. The fault is cleared after UVH pin rises above 1.0 V. Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device. RSENSE Q1 C1 SENSE– VEE GATE VIN SENSE+ ADM1075 –48V RTN (0V) RSHUNT UVH UVL OV –48V + – + – + – GATE ENABLE LOGIC 1V 0.9V 1V Figure 51. Undervoltage and Overvoltage Supply Monitoring The maximum rating on the UVH pin is 4 V and the UVH threshold is 1 V. This limits the maximum input voltage to minimum input voltage ratio to 4:1. For example, if the UVH threshold is set at 20 V, the maximum input voltage is 80 V so as not to exceed the maximum ratings of the pin. If a wider input range is required, some protection circuitry is required on the UV pins to limit them to less than 4 V. PWRGD The PWRGD output indicates the status of the output voltage. As shown in , the Figure 52 PWRGD output is derived from the DRAIN pin voltage. It is an open-drain output that pulls low when the voltage on DRAIN is less than 2 V and the GATE pin voltage is near its 12 V rail (power good). When a fault occurs or hot swap is turned off, the open-drain pull-down is disabled, allowing PWRGD to go high (power bad). PWRGD is guaran- teed to be in a valid state for VIN ≥ 1 V. FET DRAIN HOT SWAP DISABLE SIGNAL DIODE CLAMPS DRAIN TO 2V S R Q Q RDRAIN IDRAIN = 50µA MAX DRAIN 2V 11V GATE PWRGD Figure 52. Generation of PWRGD Signal DRAIN Because the source of the FET is always at or near the most negative system supply, the drain voltage is a close approxima- tion to the VDS of the FET. When the voltage at the DRAIN pin is less than 2 V, it is assumed the FET is turned on. The DRAIN pin is used by the power-good circuitry to determine when PWRGD can be asserted. A resistor is required on the DRAIN pin to limit current on the pin to 50 μA. A 2 MΩ resistor is suitable to limit the current in most cases. SPLYGD The SPLYGD output indicates when the input supply is within the programmed voltage window. This is an open-drain output. An external pull-up resistor is required on this pin. LATCH The LATCH output signals that the device has latched off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the section for additional details. Hot Swap Fault Retry SHDN The SHDN pin is a level-triggered input that allows the user to command a shutdown of the hot swap function. When this input is set low, the GATE output is switched to VEE to turn the FET off. This pin has an internal pull-up of approximately 8 μA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. Care should be taken if using the SHDN pin as an on/off pin. Pulling the SHDN low always turns off the gate. However, taking SHDN high again turns on hot swap only if there have been less than seven faults/shutdown events within a 10 second period. The retry scheme is configured to set GPO2/ALERT2 low after seven faults. The SHDN pin cannot clear the GPO2/ ALERT2 fault. The retry counter is cleared after 10 seconds of power good. Therefore, this is not an issue if there is never going to be more than seven SHDN events within a 10 second period. The UVH or UVL pin may work better as a system on/off pin if required. Toggling the UVx pin clears any faults (including GPO2/ALERT2 low after seven retry attempts). A switch shorting UVH or UVL to VEE works as an on/off switch. RESTART The RESTART pin is a falling edge triggered input that allows the user to command a 10 second automatic restart. When this input is set low, the gate turns off for 10 seconds, and then powers back up. The pin is falling edge triggered; therefore, holding RESTART low for more than 10 seconds generates only one restart. This pin has an internal pull-up of approximately 8 μA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details. |
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