Preliminary Technical Data

ADuCM360/ADuCM361

Rev. Pr R| Page 9 of 21

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

From MCU Power-Down

(mode 1, 2 and 3)

Fclk is the Cortex-M3 core clock

3-5 x Fclk

From TOTAL-HALT or

HIBERNATE (mode 4 or mode

5) mode

30.8

μs

POWER REQUIREMENTS

Power Supply Voltages

VDD

1.8

3.6

V

Power Consumption

MCU clock rate = 16 MHz, all

peripherals on

5.5

mA

MCU clock rate = 500 KHz, Both

ADCs on (Input buffers off) with

PGAs Gain = 4, 1 x SPI on, all

timers on

1

mA

Full temperature range

HIBERNATE (mode 5)

4

10

μA

Reduced temperature range

−40°C to +85°C

2

5

μA

PGA enabled – total, G>=32

320

μA

PGA

G=4/8/16 – PGA only

130

μA

G=32/64/128 – PGA only

180

Input Buffers

2 x Input buffers is 70uA

70

μA

Digital Interface +

Modulator

70

μA

Input buffers off, G=4/8/16 only

200

μA

External Reference Input

buffers

60uA each

120

μA

1

These numbers are not production tested but are guaranteed by design and/or characterization data at production release.

2

Tested at gain range = 4 after initial offset calibration.

3

Measured with an internal short. A system zero-scale calibration removes this error.

4

A recalibration at any temperature removes these errors.

5

These numbers do not include internal reference temperature drift.

6

Factory calibrated at gain = 1.

7

System calibration at a specific gain range removes the error at this gain range.

8

Measured using the box method.

9

Input current measured with one ADC measuring a channel. If both ADCs measure the same input channel, then the input current will increase – approximately

double

10

Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.

11

Endurance is qualified to 20,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.

12

13

Voltage input levels only relevant if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface will determine the

common mode voltage.

14

Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7mA.

15