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Q67100-H5164 Datasheet(PDF) 10 Page - Siemens Semiconductor Group |
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Q67100-H5164 Datasheet(HTML) 10 Page - Siemens Semiconductor Group |
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10 / 41 page  SDA 5650/X Semiconductor Group 10 02.97 2.2.2 Chip Address There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table: 2.2.3 Write Mode For writing to the PDC decoder, the following format has to be used: Description of Data Transfer (Write Mode) Step1: In order to start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses. Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. Step 4: The controller transmits the data byte to set the Control register Step 5: The slave acknowledges the reception of the byte. Step 6: The master concludes the data communication by generating a Stop Condition. The write mode is used to set the I2C-Bus control register which determines the operating mode: CS0 Input Write Mode Read Mode Low 20 (hex) 21 (hex) High 22 (hex) 23 (hex) Start Chipaddress and Write Mode AS Byte to set Control Register AS Stop |
Similar Part No. - Q67100-H5164 |
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